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? semiconductor components industries, llc, 2006 february, 2006 ? rev. 0 1 publication order number: and8242/d and8242/d 19 v, 3.0 a universal input ac?dc adaptor using ncp1271 prepared by: kahou wong on semiconductor introduction this application note presents an example circuit in figure 1 using ncp1271 (65 khz version) in the flyback topology with the design steps and measurement. the measurement shows that the 19 v, 3.0 a circuit delivers above 85% from universal input (85 to 265 vac). the no load standby consumption is 83 mw at 230 vac. the ncp1271 is one of the latest fixed?frequency current?mode pwm switching controllers with (1) soft?skip standby operation for low?level audible noise (2) integrated high?voltage startup for saving pcb space and power (3) adjustable skip level to minimize standby power and (4) optional external latch protection features. table 1 summarizes all features of an ncp1271 based power supply. figure 1. application circuit schematic ic1 ncp1271a + ? 85 to 265 vac 19 v / 3 a common mode choke d8 mbr3100 r1 100k / 2w r5 34.8k e3506?a d6 mra4005t3 1n5406 x 4 d7 murs160 r7 511 c8 2200 uf d9 1n5358b (22v@50ma) ic2 sfh615aa?x007 r9 1.69k c3 82uf / 400v ic4 tl431 q1 spp06n80c3 0.2 / 1w d5 mmsz914 c4 100uf r2 10 d10 mzp4746a (18v) r10 8.87k c9 2200 uf c10 2200 uf r6 10 ic3 sfh615aa?x007 c5 10 nf flyback transformer : cooper ctx22?17179 lp = 180uh, leakage 2.5uh max np : ns : naux = 30 : 6 : 5 hi?pot 3600vac for 1 sec, primary to secondary hi?pot 8500vac for 1 sec, winding to core c12 0.15 uf c7 1.2 nf c6 1.2 nf c2 0.1 uf t1 c1 0.1 uf d1 ? d4 r12 2.37k r11 15.8k r13 25 c11 1nf/ 1000v r8 r3 200 fuse 2a c13 100uf application note http://onsemi.com
and8242/d http://onsemi.com 2 table 1. features of power supply using ncp1271 operation mode features topology ccm/dcm flyback ? fixed?frequency current?mode control/inherent primary current limitation. ? frequency jittering to soften emi signature. ? adjustable skip duty (the borderline duty between skip operation and normal fixed?freq pwm operation). ? built?in soft?start. ? output short?circuit fault detection implemented by an internal timer that allows usage of bad coupling transformer. ? integrated high voltage startup that minimizes pcb spacing and loss. standby condition soft?skip operation ? it offers excellent low standby power consumption. ? it offers low level of low?frequency audible noise. ? the soft?skip operation will be disabled if an abrupt transient load is applied from standby operation. fault condition double hiccup restart ? it minimizes power dissipation in fault and allows auto?recovery ability when fault is cleared. latch protection activated latched off ? v cc stays above typical 5.8 v and pwm drive output remains off until circuit reset. ? reset needs the ac input unplugged. design steps step 1. define the specification input 85 to 265 vac, 50 hz output 19 vdc, 3.0 a, isolated features excellent standby performance output overvoltage protection latch a discontinuous conduction mode (dcm) flyback is the best choice here for (1) best stability and smallest inductor (i.e., fewer leakage inductance and smaller size), (2) few circuit components. step 2. biasing the controller due to the integrated high?voltage startup pin (pin 8) of the ncp1271, the initial ic supply voltage, v cc , can be obtained by connecting this pin to the high voltage dc source in figure 2. in order to have extremely low standby power consumption, the bias supply voltage, v cc , must be supplied by an external circuit that costs only one more output from the flyback. figure 2. v cc biasing scheme rectified input output 19v / 3a ncp1271 hv v cc 16 v the application range of the bias supply voltage v cc of ncp1271 is from (10 v min) and (20 max). an 18 v clamping zener is usually with 5% tolerance (i.e., 17.1 v min., 18.9 v max.). when the circuit is in standby mode, the main output voltage stays in high level because of no current consumption, but the bias supply voltage goes lower because of the consumption of the controller. hence, the biasing voltage cannot be too low and it is selected as v cc = 16 v. the 16 v bias supply voltage is made by a 6:5 turn ratio between the main output and auxiliary winding representing 19v:16v. step 3. generic flyback calculation the calculation can be made by the excel spreadsheet in (http://www.onsemi.com/pub/collateral/ncp1271sheet. xls). this section describes the details. step 3a. define the flyback basic parameter the flyback itself is a dc?to?dc converter. an estimated rectified input voltage to supply to the circuit is required. it is generally assumed that the rectified input voltages are from 100 to 400 v that covers the rectified universal ac input range. v in(l) = 100 v v in(h) = 400 v with the output voltage v out = 19 v and output diode drop v d = 1.0 v. the design here is using the 65 khz version of ncp1271. f = 65 khz step 3b. define the transformer turn ratio the maximum allowable duty of the ncp1271 is (75% min, 85% max) and the skip duty (borderline duty between normal operation and skip mode operation) is externally adjustable. that is the design constraint in the transformer
and8242/d http://onsemi.com 3 turn ratio (n1/n2). the continuous conduction mode (ccm) lossless flyback is with the following basic conversion equation. v out v d v in n 2 n 1 d 1?d (eq. 1) v in is the input voltage. v out is the output voltage. d is the duty ratio. rearrange the equation, it gives: d n 1 n 2 (v out v d ) v in n 1 n 2 (v out v d ) (eq. 2) with the assumption that the primary?to?secondary turn ratio n 1 /n 2 is 5. it gives 20% and 50% duty ratio at high and low line conditions respectively that are well within the allowable duty ratio constraint and the worst?case mosfet and diode stress are acceptable. n 1 /n 2 = 5 d high_line n 1 n 2 (v out v d ) v in n 1 n 2 (v out v d ) (eq. 3) 5(19 1) 400 5(19 1) 20% d low_line n 1 n 2 (v out v d ) v in n 1 n 2 (v out v d ) (eq. 4) 5(19 1) 100 5(19 1) 50% v mosfet v in n 1 n 2 (v out v d ) (eq. 5) 400 5(19 1) 500 v v diode v out n 2 n 1 v in 19 1 5 400 99 v (eq. 6) it is a trade?off here in picking the appropriate turn ratio. lower the diode stress v diode always comes with higher the mosfet stress v mosfet . it is noted that the reflected mosfet stress here excludes the consideration of the leakage inductance that will be covered later. the diode stress is a little bit close to 100 v limitation of mbr3100 but that is okay since 400 v input voltage will not exist in real application. step 3b. define the primary current limit the primary current limit (or the peak current) i pk directly limits the maximum power that the circuit can be transferred. in flyback topology, the input current is always discontinuous and it conducts when duty is on. hence, the maximum input power with zero current ripple (infinity inductance) is 200 w at low line 100 v when i pk = 4.0 a. that is the worst case. it is enough for the 57 w (19 v 3.0 a) output power and the 200 w will be reduced when it goes to finite inductance and dcm later. i pk = 4.0 a p in(max) = d v in i pk = 50% 100 4 = 200 w step 3c. define the primary inductance the inductance l selection is based on the fundamental inductor equation v = l di/dt. 400 20% 465 10 3 307.7 h (eq. 7) l high?line, ccm, lossless v in d i pk f 100 50% 465 10 3 192.31 h (eq. 8) l low?line, ccm, lossless v in d i pk f in order to have the circuit operate in dcm, the inductor is selected smaller than the above reference. l = 180 h step 3d. dcm parameter study figure 3. dcm magnetizing current f d 2 d magnetizing current time f f 1 based on the defined inductor l and peak current i pk , the duty ratio d of the dcm operation can be obtained by the v = l di/dt equation again. d high?line i pk fl v in (eq. 9) 465 10 3 180 10 ?6 400 11.7% d low?line i pk fl v in (eq. 10) 465 10 3 180 10 ?6 100 46.8% the equation of dcm flyback is: v out v in n 2 n 1 d d 2 (eq. 11) based on this equation, the discharge duty d 2 is calculated. d 2?high?line v in v out v d n 2 n 1 d (eq. 12) 400 11.7% (19 1) 5 46.8%
and8242/d http://onsemi.com 4 d 2?low?line v in v out v d n 2 n 1 d (eq. 13) 100 46.8% (19 1) 5 46.8% hence, the dcm operation is confirmed here for d + d 2 < 100%. in an ener gy perspective, the total maximum input power in dcm is 93.6 w. that is more than enough (at 57 w/93.6 w = 60.9% efficiency) to deliver the required output power of 3.0 a 19 v = 57 w. p in 1 2 li 2 f 1 2 180 10 ?6 4 2 65 10 3 93.6 w (eq. 14) step 3e. snubber calculation the objective of flyback snubber is to limit the transient voltage stress on the mosfet because of transformer leakage inductance. hence, the calculation starts with the leakage inductance. from the transformer specification, the maximum leakage inductance is 2.5 h. when the leakage inductance is charged with the peak current 4.0 a, the maximum possible power to be stored there is 1.3 w. p snubber 1 2 l leakage i pk 2 f (eq. 15) 1 2 2.5 10 ?6 4 2 65 10 3 1.3 w if a 2?watt 100 k snubber resistor is used to dissipate this 1.3 w, the voltage across this snubber resistor will be 360.6 v. p snubber v snubber 2 r snubber (eq. 16) v snubber p snubber r snubber (eq. 17) 1.3 100 10 3 360.6 v thus, the maximum mosfet stress due to the leakage inductance will be 400 + 360.6 = 760.6 v and it is under the 800 v maximum allowable limit. the minimum capacitor to deliver this power will be 307 pf. a 10 nf capacitor is used here. p snubber 1 2 c snubber v snubber 2 f (eq. 18) c snubber 2p snubber v snubber 2 f 21.3 360.6 2 65 10 3 307 p f (eq. 19 ) step 4. special setting on ncp1271 circuit this section describes how to set the circuit parameter in the circuit using ncp1271. step 4a. optional output ovp latch figure 4. output overvoltage protection scheme 1 2 3 4 8 6 5 ncp1271 opto coupler v out r5 d10 r3 200 d9 c4 r13 25 1n5358b (22v @ 50ma) mzp4746 34.8k 1.2 nf (18 v) figure 4 shows the output overvoltage protection (ovp) latch circuit. when output voltage is too high, a current from the optocoupler pulls high the latch pin (pin 1) voltage and eventually latches off the controller. in implementation, the zener diode, d9 1n5358b, has a leakage current 50 ma at 22 v. it means that there is an up?to?50?ma current flowing through the zener when the biasing voltage is somewhere below 22 v. this leakage current can let the optocoupler conducts and triggers the ovp latch even if the voltage is below the ovp threshold. in order to prevent it, a r13 resistor is added to bypass the leakage current. the typical optocoupler diode forward voltage drop is 1.25 v and the value of r13 is 1.25 v 50 ma = 25 . hence, the ovp threshold includes the zener biasing voltage 22 v (with 5% tolerance) and the optocoupler input diode forward bias voltage (1.25 v typical). as long as it is lower than the 25 v rating of the output capacitor, it?s fine. the latch threshold is 8.0 v. when pin 1 is opened for default 1.0 v skip level, the pin 1 voltage is tied to the internal bias voltage of the ncp1271. that is typically 6.5 v. when a r5 34.8 k skip resistor is used, the nominal pin 1 voltage goes down to 34.8 k 43 a = 1.5 v. hence, it is always recommended to put a skip resistor on pin 1 to make sure that there is a good margin between the 8.0 v latch threshold and the nominal pin 1 voltage to prevent fault triggering due to noise or leakage current from the latch protection circuit. in addition, an nf?order capacitor is generally added to the latch protection pin to increase noise immunity there. in order to pull the pin 1 voltage above the 8.0 v (typical) latch threshold, a greater?than?8.0?v source is needed. that is
and8242/d http://onsemi.com 5 usually the bias supply voltage v cc . hence, the optocoupler is connected to the v cc source that can be as high as 18 v ( 5%). in order to protect pin 1, a 200 is connected to limit the current below the maximum allowed 100 ma. in addition, an internal esd diode will limit the maximum voltage on pin 1 in 10 v without damage. figure 5. output ovp testing figure 5 shows how the pin 1 voltage reacts when the output voltage is connected to a 24 v source. it can be seen that the voltage jumps up and clamps to 10.5 v from the nominal 1.5 v (34.8 k 43 a) when the output voltage is over 23 v typically. once the voltage is over the 8.0 v latch threshold, the circuit goes latch off. step 4b skipping adjustment the skip resistor, r5, provides two functions: (1) the setting of the skip duty that the borderline duty between the normal and skipping operation; (2) and the optimization of the standby power consumption; (3) and indirectly increase the latch?off immunity by lowering the pin 1 voltage. due to the soft?skip mode standby operation. the low?frequency audible noise is not a critical issue here. basically, the skip level (or skip duty) is set to be as high as possible because higher value can save more power by allowing more skipping period during standby. the skip?level upper limit is limited by the skip duty of the flyback, because it is not desirable to enter skip mode operation in full load or nominal condition. when r5 = 34.8 k , the skip level is r skip = 0.338 v that corresponds to skip duty d skip = 9%. the 9% skip duty is below the nominal operating duty range (11.7% to 46.8% in step 3d) and hence the circuit does not skip in full load or nominal condition. v skip (r skip i skip ?1.25 v)
0.73 0.338 v (eq. 20) d skip v skip 3v d max 0.338 3 80% 9% (eq. 21) step 4c. maximum primary current setting current sense resistor, r8, provides two functions: (1) current sensing for current?mode operation; (2)and the maximum primary current limitation. when the voltage exceeds 1.0 v, the pwm output goes low because of overcurrent condition. when r8 = 0.2 , the maximum allowable current is 5.0 a that is greater than the required 4.0 a in step 3b. i d, max 1v r cs 1v 0.2 5a 4a (eq. 22) step 4d. maximum allowable duty setting and stability/transient response the ramp resistor, r7, provides two functions: (1) compensation ramp function in current?mode operation; (2) and reduce the maximum duty when it is above 10 k . higher ramp resistor value means more compensation ramp in the modulation. it also means the modulation method becomes more voltage?mode (or voltage?loop depended) and less current?mode (or current?loop depended). it results in slower transient response, but better stability. if better transient response is wanted, more current?mode modulation is needed, and the ramp resistor value is low that makes higher loop gain. on the other hand, if better stability is wanted, fewer current?mode modulation is needed and the ramp resistor is high that makes slow voltage?loop response but better stability. figures 6 and 7 shows the transient response of the circuit recovering from standby (output current = 0 a) to full load (output current = 3.0 a) with different values of r7. the output current is 1.0 a/div changing from 0 a to 3.0 a in green color. the output volt ages are ac?coupled, 200 mv/div, and 2.0 v/div respectively. the input voltage is 110 vac. it shows that the transient response with low ramp resistor, r7, value is better. figures 6 and 7 also explain why the ramp resistor is below 10 k because the transient can be bad otherwise. figure 6. transient response with r7 = 511
and8242/d http://onsemi.com 6 figure 7. transient response with r7 = 2.0 k the maximum allowable duty is 80% when ramp resistor, r7, is smaller than 10 k . now that r7 = 511 and the maximum allowable duty is 80% that covers the operating duty (11.7% to 46.8% in step 3d). step 4e. hv?vcc reverse diode the diode, d6, is a standard protection of the hv pin (pin 8). when the main power is interrupted in application, the hv pin voltage may potentially go negative in a short transient period. it creates a reverse current that goes out of the hv pin and the current can damage the device. the inserted diode turns on when the hv pin voltage goes below the v cc biasing voltage, and hence eliminate the chance of negative voltage on the hv pin or the reverse current. step 4f. decoupling capacitors there are three pins in the ncp1271 that may need external decoupling capacitors. 1. skip/latch pin (pin 1) ? if the voltage on this pin is above 8.0 v, the circuit goes latch off. hence, a decoupling capacitor on this pin is essential to increase noise immunity there. 2. feedback pin (pin 2) ? in order to save current consumption, the feedback pin sinking current in a?order is very easy to get polluted in a noisy switch?mode power?supply environment and the circuit operation may be affected. 3. v cc pin (pin 6) ? the ncp1271 maintains normal operation when v cc is above v cc(off) (9.1 v typical). if v cc drops below v cc(off) by switching noise, the circuit wrongly recognizes it as a fault condition. hence, it is important to locate the v cc capacitor or additional decoupling capacitor as close as possible to the ncp1271. step 5. auxiliary supply figure 8 shows the auxiliary supply circuit. there is a resistor to increase flexibility to further redesign the circuit for other higher output voltage by dumping the extra bias supply voltage across the resistor. figure 8. auxiliary supply ncp1271 c4 100uf r2 10 c13 100uf step 6. layout consideration figures 9?10 show the layout of the design. it is a single?layer pcb. r4 is a cancelled component in order to save some extra standby power consumption. the major concerns are the following. 1. to minimize the high?current loop and locate the ic controller outside the high?current loop to prevent malfunction of the ic internal logic due to strong magnetic field from the high current. 2. to locate the decoupling capacitors closely to the device to improve noise immunity. 3. to locate the v cc capacitor very close to the device to prevent the circuit enter fault condition because of noise. 4. to locate the output voltage sense resistor closely to the output load points. 5. to minimize the current sense trace that is low?impedance and easily polluted. 6. to minimize the distance between the feedback opto coupler and controller because the trace is easily polluted. 7. to minimize the distance between the mosfet and controller because the pcb trace is high frequency and high current that it can easily pollute other part of the circuit. it can be observed that the electrolytic through?hole vcc capacitor is located exactly on the top side where the so?7 controller is located on the bottom side. that minimizes the vcc pin noise that may potential lead the controller to fault condition.
and8242/d http://onsemi.com 7 figure 9. top view figure 10. bottom view measurement part i. standby performance the circuit offers excellent no load standby performance. the 230?vac power consumption of the 57 w circuit is 83 mw. when input is 230 vac and output is 503 mw (19.13 v 26.3 ma), the input power is 710 mw. figure 11. standby pulse
and8242/d http://onsemi.com 8 figure 11 shows a typical soft?skip pulse train during the standby operation. the yellow trace is the cs pin (pin 3) voltage at 200 mv/div. the orange trace shows the duty that comes from 0% to 2.27%. the figure shows that the soft?skip time is not effectively 300 s. in the figure, the first five switching cycles, for about 80 s, are in a soft?skip period where the duty is gradually increasing. then, the duty follows the feedback voltage variation because the soft?skip reference voltage is higher than the divided?by?3 feedback voltage. it is described in figure 34 of the data sheet. part ii. normal operation table 2 shows the full load efficiency of the circuit is above 85%. table 2. normal operation performance input output efficiency 85 vac 66.4 w 19 v 3.0 a 85.8% 110 vac 65.4 w 19 v 3.0 a 87.2% 120 vac 65.4 w 19 v 3.0 a 87.2% 180 vac 65.2 w 19 v 3.0 a 87.4% 220 vac 65.2 w 19 v 3.0 a 87.4% 230 vac 65.2 w 19 v 3.0 a 87.4% 265 vac 65.2 w 19 v 3.0 a 87.4% part iii. dynamic study figure 12. startup transient figure 12 shows the startup transient waveforms of the circuit when input is 110 vac. looking from the top right side, the yellow trace is the output voltage in 5.0 v/div. the red trace is the v cc voltage in 5. 0 v/div. the green trace is the feedback pin voltage in 1.0 v/div. the blue trace is the voltage across current sense resistor r8 in 500 mv/div representing the drain current. the waveforms are captured when v cc reaches v cc(on) (i.e., red trace reaches 12.6 v). a beginning 5.0 ms soft?start is observed in the drain current. the green trace v fb drops below 3.0 v after 32 ms that is shorter than the 130 ms fault validation time and hence the circuit does not enter fault condition and able to maintain in the normal operation condition. figure 13. operating to standby figure 13 shows the go?to?standby transition from full load operation. the output voltage does not consume current and remains at 19 v, but the v cc voltage drops from 16 v to 15 v because the v cc auxiliary winding still supplies current to the controller. the minimum v cc voltage in the transition can be 12 v. that explains why the 16 v biasing voltage is selected and a pair of 100 f v cc capacitor is needed to maintain v cc above v cc(off) (9.1 v typical) in order to prevent v cc reset. conclusion a 19 v/3.0 a flyback circuit using ncp1271 is presented. because of the pwm controller, ncp1271, the circuit of fers low?audible?noise soft?skip mode operation, excellent standby performance, and output overvoltage protection latch. the design consideration of most components in the design is explained. the design procedure is also summarized in an excel spreadsheet in http://www.onsemi.com. when design with the ncp1271, special care on (1) locate a decoupling capacitor on the latch/skip pin (pin 1) in order to prevent fault latchoff due to noise and (2) locate the vcc capacitor very close to the controller in order to prevent entering fault condition due to noise.
and8242/d http://onsemi.com 9 appendix i. bill of material for the ncp1271 19 v/3.0 a example circuit designator qty part number description manufacturer t1 1 e3506?a 3.0 a 508 h common?mode filter coilcraft t2 1 ctx22?17179 custom transformer 180 h 30:6:5, 2.5 h max leakage cooper/coiltronics ic1 1 ncp1271d65r2 65 khz flyback pwm controller, so?7 on semiconductor ic2 1 tl431aid 2.5 v 1% voltage reference, so?8 on semiconductor ic3?ic4 2 sfh615aa?x007 optocoupler vishay d1?d4 4 1n5406 3.0 a 600 v diode, axial 267?05 on semiconductor d5 1 mmsz914 1.0 a 100 v diode, sod?123 on semiconductor d6 1 mra4005t3 1.0 a 600 v diode, sma on semiconductor d7 1 murs160 1.0 a 600 v diode, smb on semiconductor d8 1 mbr3100 3.0 a 100 v schottky diode, axial 267?05 on semiconductor d9 1 1n5358b 22 v @ 50 ma zener diode on semiconductor d10 1 mzp4746a 18 v @ 14 ma zener diode on semiconductor q1 1 spp06n80c3 6.0 a 800 v n?mosfet, to?220ab infineon r1 1 p100kw?2bk 100 k 2.0 w, axial 5% digi?key r2 1 cfr?25jb?10r 10 , 1/4 w axial yageo r3 1 crcw12062000f 200 , 1206 vishay r4 1 (deleted) n/a n/a r5 1 crcw12063482f 34.8 k , 1206 vishay r6 1 crcw120610r0f 10 , 1206 vishay r7 1 crcw12065110f 511 1206 vishay r8 1 wsl2512r2000fea 0.2 1.0 w 1% vishay r9 1 crcw12061691f 1.69 k , 1206 vishay r10 1 crcw12061502f 15 k , 1206 vishay r11 1 crcw12061582f 15.8 k 1206 vishay r12 1 crcw12062371f 2.37 k 1206 vishay r13 1 crcw120624r9f 24.9 , 1206 vishay c1?c2 2 phe840ma6100ma04 0.1 f x2 cap 10 mm pitch evox rifa c3 1 ecos2gp820ba, eeted2g820ba, or eetxb2g820ba 82 f 400 v electrolytic panasonic c4, c13 2 eca1em101 100 f 25 v electrolytic panasonic c5 1 630mmb103j 10 nf 630 v film cap rubycon c6?c7 1 vj1206y122kxxa 1.2 nf 25 v, 1206 vishay c8?c10 3 025yxg220m12.5x30 2200 f 25 v electrolytic rubycon c11 1 ero610rj4100m 1.0 nf 1.0 kv 5.0 mm pitch y2 cap evox rifa c12 1 vj1206y154kxxa 0.15 f 25 v ceramic vishay fuse 1 1025td2?r 250 v 2.0 a tie delay fuse cooper fuse heatsink 1 590302b03600 heatsink for to?220 package aavid heatsink insulation 1 4672 to?220 mica insulation keystone ac connector 1 770w?x2/10 iec60320 c8 connector qualtek dc connector 1 26?60?4030 or 009652038 3?terminal 3.96 mm pitch male header molex standoff 4 4804 k standoff m/f hex 4?40 nyl 0.750? digi?key heatsink mechanic 1 30f698 4?40 1/4 inch screw newark heatsink/standoff mechanic 5 31f2106 4?40 screw nuts newark
and8242/d http://onsemi.com 10 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 and8242/d literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082?1312 usa phone : 480?829?7710 or 800?344?3860 toll free usa/canada fax : 480?829?7709 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.

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